A NAND-type of flash memory is well-known as an electrically rewritable and nonvolatile semiconductor memory device. The demands for the NAND-type of flash memories are increased more and more in accordance with the capacity increase and the multi-level storage scheme installed.
Data program (or write) of the NAND-type flash memory is performed in such a manner as to apply program voltage to a selected word line, thereby injecting electrons into the floating gate of a selected cell (i.e., “0”-program cell) from the cell channel. In accordance with the electron injection, the selected cell's threshold voltage becomes high in the positive direction.
In the data program sequence, one page data are programmed simultaneously. In a “1”-program cell (i.e., program-inhibited cell), in which the threshold voltage is not to be increased, the cell channel is preliminary set in a floating state and boosted in potential by capacitive coupling from the word lines when applying the program voltage, so that electron injection into the floating gate may be prevented. Therefore, at the beginning of the program sequence, it is in need of initially charging-up the one page cell's channels by use of bit line voltage control.
In detail, the initial charging of the cell's channels is performed as follows: “1”-program cell's channel is charged-up to the power supply voltage “Vdd” via a bit line, and set in a floating state; and “0”-program cell's channel is set at the ground voltage “Vss” via another bit line. According to this initial charging operation for the bit lines and cell's channels coupled thereto, when applying a program voltage and a program-pass voltage to the selected word line and non-selected word lines, respectively, it is executed such a program control that electron injection occurs in the “0”-program cell because large voltage is applied between the floating gate and the cell channel while electron injection does not occur in the “1”-program cell because the cell channel is boosted in potential by capacitive coupling from the word lines.
In order to prevent “1”-program cells and non-selected cells from being erroneously programmed, it is material to efficiently boost the cell's channels. Therefore, there have been provided various kinds of self-boost technologies (for example, refer to Japanese Patent Application Publication No. P2009-70461A).
In a product with the power supply voltage of about Vdd=2.5V, it is sufficiently able to do the initial cell's channel charging operation at the beginning of the program sequence. However, in a low power supply voltage case such as Vdd=1.8V (for example, in case of a mobile product), the initially charged cell's channel stays at 1.8V, and it is insufficient to boost the cell channel efficiently. This causes the memory device to be program-disturbed.
Even if the power supply voltage is low, preparing a boost circuit, it becomes possible to boost efficiently the cell's channel. However, in a flash memory having a large page length, for example, of 2 kByte, the total bit line capacitance for one page cells to be programmed simultaneously becomes, for example, 3 nF. Therefore, the boost circuit area necessary for charging-up the bit lines becomes large, and the power consumption also becomes large.
In the above-described Japanese Patent Application Publication No. P2009-70461A, there is disclosed a method for efficiently channel-boosting, in which a selected bit line preset at Vdd is boosted by capacitive coupling from the p-type well, non-selected bit lines and the cell source line.